1. Field of the Invention
The present invention relates to an improved multilayer circuit board and a method of manufacture therefor. More particularly, the invention relates to a multilayer circuit board having circuit cores coated with a conformal layer of insulating material to reduce the risk of failures caused by impurities trapped during lamination, and a method of manufacture therefor.
2. Description of the Related Art
Multilayer circuit boards are typically manufactured by first fabricating individual circuit cores, stacking the circuit cores in a parallel relationship with insulating layers between each pair of circuit cores, and then laminating the assembly together. A circuit core may be an insulating substrate having a conductive circuit pattern on one or both sides, or may be a single sheet of conductor having perforations therein to provide the circuit pattern. The circuit patterns are formed on the surface of an insulating substrate by selectively plating or selectively etching using a photoresist, which is removed after the circuit patterns are formed. The circuit patterns are formed on single sheets of conductor by drilling or punching holes in a unique pattern.
Critical defects in a multilayer circuit board may arise during lamination of the circuit cores. During lamination, material from the insulating layers flows into and fills the spaces between the conductive elements of the circuit patterns. The problems become particularly acute when the space between the conductive elements approaches or is less than 0.0055 inches. Impurities from the insulating layers and the environment can be trapped into the circuit board. The impurities are either particles or surface contaminants. These impurities are known to later cause failures of the circuit board. The failures may be characterized as either intralevel or interlevel shorts resulting from impurities having insufficient dielectric properties. Intralevel shorts are those between circuit lines of the same circuit plane, or between circuit lines and plated thru holes interconnecting the circuit planes. Interlevel shorts are those between different circuit planes.
As the demand for improved circuit performance increases, the density of circuit lines in the conductive circuit pattern also increases. As the density of circuit lines increases, the average spacing between the circuit lines decreases, thereby increasing the risk of failures caused by shorting. Thus, modern demand for improved circuit performance has resulted in the recognition of a need to reduce the risk of failures caused by impurities trapped during lamination.
One technique which reduces the risk of failures caused by impurities trapped during lamination involves the use of permanent photoresists. The layers of photoresist are not removed following the formation of the conductive circuit patterns of the circuit planes. Instead, the photoresist remains permanently on the substrates and in the final laminated structure. The presence of the permanent photoresist during lamination reduces the likelihood of impurities being trapped in the spaces between the circuit lines during lamination and thereby bridging adjacent circuit pattern elements. However, while permanent photoresists fill in the spaces between the circuit lines, the top or bottom surfaces of the circuit lines remain exposed and impurities trapped during lamination may still cause short circuits. In addition, multilayer circuit boards manufactured with permanent photoresists suffer from unique defects not related to the trapping of impurities during lamination. More particularly, the necessity of providing photosensitivity in a layer allowed to remain in the final structure of the circuit board increases material and processing costs, and may also degrade the mechanical and electrical properties of the material.
Another technique which reduces the risk of failures caused by impurities trapped during lamination involves fabricating the individual circuit cores by laminating together sheets of dielectric material and sheets of pre-punched conductive material. The sheets of dielectric material are sandwiched between separate sheets of the pre-punched conductive material. The conductive material is pre-punched according to the desired conductive circuit patterns. During lamination, the dielectric material flows into the holes punched in the conductive sheets to form a flush surface laminate circuit core. Several circuit cores are then finally laminated together with insulating layers therebetween, as in the usual manner. The absence of spaces between the circuit lines during lamination reduces the likelihood of impurities being trapped and thereby bridging adjacent circuit pattern elements. Again, however, the top or bottom surfaces of the circuit lines are exposed during final lamination. Thus, impurities trapped during final lamination may still cause short circuits.